The present invention relates to a power amplification circuit, in particular to a power amplification circuit having a wide band frequency characteristic.
A power amplification circuit performs a power amplification of a weak signal to a necessary level, and outputs the amplified signal. For example in wireless communication use as exemplified by a portable device, such a power amplification circuit is utilized in order to amplify a weak high frequency signal to a signal with a sufficient power which a wireless system requires in outputting.
One example of the power amplification circuit includes a differential push-pull method. A power amplification circuit according to the differential push-pull method combines by a combiner a differential signal amplified by a pair of transistors, and generates an output signal. Since a differential signal is utilized, an output twice as high in amplitude as an output signal of a single transistor is obtained, and in addition, even harmonics are balanced out. Therefore, the differential push-pull method provides a means effective in realizing an amplification circuit of high power and low distortion.
In mobile communications fields as typified by a mobile-phone, realization of low cost when practicing reduction of occupied area is an important subject. Therefore, as a component transistor, a miniaturized CMOS transistor (complementary insulated-gate field effect transistor) is utilized, and as a combiner in a microwave region, a transformer is used frequently. An example of configuration of a differential push-pull amplifier utilizing such miniaturizing CMOS process is described in Non Patent Literature 1 (Jongchan Kang, et al., “A single-chip linear CMOS power amplifier for 2.4 GHz WLAN”, International Solid-State Circuits Conference 2006, Digest of Technical Papers, pp. 761-769, February 2006).
In the configuration of the power amplifier illustrated in Non Patent Literature 1, a transformer which serves as a combiner includes a primary slab inductor and a secondary slab inductor, having a half-turn winding, respectively. Both ends of the primary metal slab are driven by one pair of MOS transistors which receive a differential signal. In Non Patent Literature 1, the primary inductor and secondary inductor of the transformer have respective inductors of a half-turn winding, and improvement of conversion efficiency (a ratio of output power Pout to input power Pin, Pout/Pin) is promoted by reducing cancellation of magnetic flux from an opposing side.
Patent Literature 1 (Japanese Unexamined Patent Application Publication (Translation of PCT application) No. 2005-503679) discloses configuration of a power amplification circuit using a differential push-pull amplifier aiming at low-loss, a small area, and high power. In the configuration disclosed by Patent Literature 1, outputs of plural differential push-pull amplifiers are combined together by a transformer, thereby realizing a several-Watt-class output with the use of miniaturized CMOS transistors. Specifically, in Patent Literature 1, the secondary inductors of the transformer are coupled in series, and the outputs of four differential push-pull amplifiers are combined together. Each of the secondary inductors performs impedance conversion and provides low output impedance to a drain of a transistor of each push-pull amplifier. Accordingly, drain voltage is suppressed low and high-output power is realized. The primary inductor and secondary inductor of the transformer are respectively formed in a slab shape, and the transformer is arranged to form a circular geometry. Accordingly, a power amplification circuit with low loss and small area is realized.
Patent Literature 2 (Japanese Unexamined Patent Publication No. 2006-295896) discloses configuration of a power amplifier aiming at improvement of the efficiency and operation region of the power amplifier. In the configuration disclosed by Patent Literature 2, a transmission line transformer used as a matching circuit of the power amplifier utilizes a primary transmission line (inductor) of a different shape. That is, primary inductors with a different shape and a different parasitic component are arranged on both sides of a secondary inductor of the transformer, and a differential push-pull amplifier is coupled to each of the primary inductors. The primary inductors are switched so that load resistance may be small when generating a high-output power, and the load resistance may be large when generating a low-output power. In Patent Literature 2, improvement of the efficiency and operation region (dynamic range) of the entire power amplification circuit are promoted by providing different output load to two differential push-pull amplifiers.    (Patent Literature 1) Japanese Unexamined Patent Publication No. 2005-503679    (Patent Literature 2) Japanese Unexamined Patent Publication No. 2006-295896    (Non Patent Literature 1) Jongchan Rang, et al., “A single-chip linear CMOS power amplifier for 2.4 GHz WLAN”, International Solid-State Circuits Conference 2006, Digest of Technical Papers, pp. 761-769, February 2006.